The present invention pertains to a reference voltage generator that generates a bias voltage or another prescribed reference voltage. In particular, the present invention pertains to a MOS type reference voltage generator.
For example, when a constant-current source is used in an analog circuit, it is necessary to apply a bias voltage or reference voltage at a prescribed voltage level from a reference voltage generator to the constant-current source.
FIG. 15 is a schematic diagram illustrating the circuit configuration of a typical conventional reference voltage generator. This reference voltage generator is composed of a pair of NMOS transistors 100, 102, a pair of PMOS transistors 104, 106, and resistor 108. The two NMOS transistors 100, 102 form a current mirror circuit, and output terminal 110 is led out from the drain of the NMOS transistor on one side, e.g., NMOS transistor 102.
At steady state, various MOS transistors 100-106 operate in saturation mode. If the current that flows through two NMOS transistors 100, 102 of the current mirror circuit is I, the voltage between the gate and source of PMOS transistor 104 is Vgs1, and the resistance of resistor 108 is R, then reference voltage Vref obtained at output terminal 110 will be given by formula (1):
Vref=VDDxe2x88x92(Ixc2x7R+Vgs1)xe2x80x83xe2x80x83(1) 
Also, current I is given by following formula (2).
I=(Ixc2xd/K2xc2xdxe2x88x92Ixc2xd/KIxc2xd)/Rxe2x80x83xe2x80x83(2) 
where, K1 and K2 are given by following formulas (3) and (4), respectively.
K1=xcexcCOX(W1/L1)/2xe2x80x83xe2x80x83(3) 
K2=xcexcCOX(W2/L2)/2xe2x80x83xe2x80x83(4) 
where, W1 and L1 represent the channel width and channel length of PMOS transistor 104, respectively, and W2 and L2 represent the channel width and channel length of PMOS transistor 106, respectively.
For this reference voltage generator, when the power is turned on, a small leakage current flows through various MOS transistors 100-106 between the terminal of power source voltage VDD on the positive electrode side and the terminal of power source voltage VSS on the negative electrode side. As a result, the gate voltage of PMOS transistors 104 and 106 gradually decreases, while the gate voltage of NMOS transistors 100 and 102 gradually increases. Consequently, once the gate voltage of said MOS transistors 100-106 reaches a potential that permits the flow of a certain drain current, the mode shifts instantly to the saturation region, and the stable operating point can be reached.
However, the aforementioned starting method that primarily depends on the leakage current of the MOS transistors requires a relatively long time from power on to reach the desired output voltage (reference voltage) Vref. As a result, this constitution is inconvenient for applications that require immediate operation directly after power on and for applications that require immediate switching from power save mode (stand-by mode) to operating mode.
In order to solve this problem, in the prior art, as shown in FIG. 16, a start-up circuit made up of NMOS transistor 112 connected as a diode is connected between the gate/drain of PMOS transistor 106 and the gate/drain of NMOS transistor 100. Due to this start-up circuit, immediately after power on, current flows from the gate/drain side of PMOS transistor 106 to the gate/drain side of NMOS transistor 100 through NMOS transistor 112. As a result, it is possible to reduce the time required for MOS transistors 100-106 to shift to the stable operating point in the saturation region.
However, for the aforementioned start-up circuit made up of active element (MOS transistor 112, not only is the circuit area significantly increased, but also the off requirements after the end of start-up become very strict, which is undesired. That is, in the stable operating state after start-up, in order to hold the off state of MOS transistor 112, the difference in potential between two nodes n1 and n2 must be higher than threshold voltage Vt of MOS transistor 112. It is very difficult to meet this off requirement in practical applications. In particular, it is almost impossible when a low power source voltage is adopted.
The purpose of this invention is to solve the aforementioned problems of the conventional methods by providing a type of reference voltage generator that can perform high-speed start-up with high stability.
Another purpose of this invention is to provide a reference voltage generator that has a start-up circuit which can be used even with a low power source voltage, without significantly increasing the circuit area.
In accordance with one aspect of the invention, a reference voltage generator has a MOS transistor which has its gate and drain short circuited to each other and has its source connected to a first power source voltage terminal that provides a first potential, a capacitor connected between the gate/drain of the aforementioned MOS transistor and a second power source voltage terminal that provides a second potential, and an output terminal connected to a prescribed node of the circuit; the aforementioned MOS transistor operates in saturation mode, and a reference voltage at a prescribed level is output from the aforementioned output terminal.
With the aforementioned constitution, when the power is turned on, due to the capacitive coupling of the capacitor, the potential at the gate/drain of the MOS transistor connected as a diode is pulled towards the side of the power source voltage opposite to the source side. As a result, the MOS transistor quickly reaches a stable operating point in the saturation region, and the overall circuit start-up time can be reduced.
For the reference voltage generator of the present invention, it is preferred that the constitution have a current mirror circuit for having a prescribed current flow in the aforementioned MOS transistor and the aforementioned node. As an embodiment in this case, the aforementioned current mirror circuit may contain the aforementioned MOS transistor.
As a preferred embodiment of the reference voltage generator in this invention, the constitution has the following parts: a first MOS transistor of a first conductivity type that has its gate and drain short-circuited to each other and has its source connected to a first power source voltage terminal that provides a first potential, a second MOS transistor of a first conductivity type that has its gate connected to the gate of the aforementioned first MOS transistor and has its source connected to the aforementioned first power source voltage terminal so as to form a current mirror circuit together with the aforementioned first MOS transistor, a third MOS transistor of the second conductivity type that has its drain connected to the drain of the aforementioned first MOS transistor and has its source connected to the second power source voltage terminal that provides the second potential, a fourth MOS transistor of the second conductivity type that has its drain connected to the drain of the aforementioned second MOS transistor and has its source connected to the aforementioned second power source voltage terminal, an offset circuit for providing voltage offsets to the gate-source voltage of the aforementioned third MOS transistor and the aforementioned fourth MOS transistor, respectively, a capacitor connected between the gate/drain of the aforementioned first MOS transistor and the aforementioned second power source voltage terminal, and a reference voltage output terminal connected to the drain of the aforementioned first MOS transistor or the aforementioned second MOS transistor.
As a modified embodiment of the aforementioned embodiment, the constitution may have a capacitor connected between the gate/drain of the aforementioned fourth MOS transistor and the aforementioned first power source voltage terminal instead of, or in addition to, the capacitor connected between the gate/drain of the aforementioned first MOS transistor and the aforementioned second power source voltage terminal.
In the aforementioned embodiments, it is preferred that the gates of the aforementioned third MOS transistor and the aforementioned fourth MOS transistor that perform the offset function be connected together, and that the gate and drain of the aforementioned fourth MOS transistor be short-circuited. Also, the following constitution is preferred: the gate of the aforementioned third MOS transistor is connected to the drain of the aforementioned fourth MOS transistor, and the gate of the aforementioned fourth MOS transistor is connected to the source of the aforementioned third MOS transistor.
For the reference voltage generator of this invention, it is preferred that the aforementioned offset circuit contain a resistor connected between the aforementioned second power source voltage terminal and the source of the aforementioned third MOS transistor or the source of the aforementioned fourth MOS transistor.